Description of the Prior Art
In the design of driver circuits for a liquid crystal display device, the life of the liquid crystal is a major consideration. When a D.C. voltage is applied to the liquid crystal over a long period of time, the life of the liquid crystal is shortened. As a result, it has become general practice to apply a bidirectional drive to the liquid crystal, as described in an article by N. A. Luce, entitled "C/MOS Digital Wristwatch Features Liquid Crystal Display" on pages 93-97 in Electronics, Apr. 10, 1972. Through this technique, the polarity of the voltage applied across the electrode of the liquid crystal is periodically changed. Moreover, the periods of time for each respective polarity are symmetrical. In the liquid crystal drive circuit, a low frequency voltage is applied during the "on" state, while a high frequency voltage is applied during the "off" state.
Also employed are liquid crystal display devices which have visual threshold voltages (Vth) as described in an article entitled, "Deformation of Nematic Liquid Crystals with Vertical Orientation in Electrical Fields" by M. F. Schiekel and K. Fahrenschon in the Applied Physics Letters, Volume 19, Number 10, Nov. 15, 1971, page 391-398 and in the Japanese technical journal "Transistor gijitsu", August 1971, 104-109. In this type of device, the visual (optical) states are changed by controlling the voltage levels in dependence upon a threshold voltage. This type of display device drive is more suitable for dynamic indications than the above-described frequency drive device.
Examples of circuitry for driving liquid-crystal display devices by three-level voltage sources are described in U.S. patent application Ser. No. 419,348, entitled, "Driving System for Liquid Crystal Display Device" filed Nov. 27, 1973 by Y. Hatsukano and Application Ser. No. 419,442 entitled "Driving System for Liquid Crystal Display Device" filed Nov. 27, 1973 by Y. Hatsukano, each application being assigned to the assignee of the present application.
An example of a voltage supplying circuit for supplying multi-level voltages to liquid crystal display devices is described in Japanese Patent Application No. 38,728 (1974) in which complementary MOS circuits are employed for achieving low power consumption. The circuitry described in this application which employs only MOSFETs, however, has problems in that the threshold voltage of some of the MOSFETs becomes higher than that of other MOSFETs (the "substrate effect"), since the semiconductor well regions of some of the MOSFETs for supplying intermediate voltage levels are connected to a potential which differs from the voltage applied to the source electrodes.
In order to eliminate this undesirable "substrate effect", a circuit of the type shown in FIG. 1a of the drawings of the present application is proposed. In this circuit, a P-type MOSFET 1 is connected to each of a plurality of N-type MOSFETs 2, 3 and 4. MOSFET 1 constitutes part of a complementary MOSFET pair connected to the semiconductor substrate. A voltage level V1 (0 volts) is applied to the source electrode of MOSFET 1 and other voltage levels (V2 = -20 volts), (v3 = -15 volts), and (V4 = -10) are applied to the source electrodes of the n-type MOSFETs 2, 3 and 4, respectively. As can be seen from the above parametric values, the voltage level V1 is the highest voltage level, the voltage level V2 is the lowest voltage level and the voltage levels V3 and V4 are intermediate voltage levels.
In the circuitry of FIG. 1a, the respective regions of the MOSFETs would be formed as shown in FIG. 1b, which is a cross-sectional view of a substrate in which respective semiconductor regions have been formed to provide the schematic circuit shown in FIG. 1a. The source electrodes of the N-type MOSFETs 3 and 4, for supplying intermediate voltage levels, are connected to the respective well regions W2 and W3. As a result, the threshold voltages of MOSFETs 3 and 4 are not higher than the threshold voltages of MOSFETs 1 and 2, i.e. the so-called substrate effect is prevented. In this semiconductor device configuration, however, when MOSFET 2 is turned "on", current flows through the N-type drain regions D3 and D4, well regions W2 and W3 of MOSFETs 3 and 4, to the respective voltage terminals V3 and V4, as shown by the curved arrows in FIG. 1b. This current flow, moreover, causes an undesirable increase in power consumption.
In order to prevent the formation of these current paths, the source electrodes of MOSFETs 3 and 4 may be disconnected from the respective p-type well regions W2 and W3. With such a circuit configuration, however, since the well regions W2 and W3 are not electrically connected to any fixed potential, the potentials therein will become unstable. As a result, the threshold voltages of MOSFETs 3 and 4 are not constant during the operation of the circuit.